This present invention relates generally to digital memory devices and systems, and more particularly to power-saving modes for such devices and systems.
Microprocessors, digital signal processors, digital imaging devices, and many other types of digital data processing devices rely on an attached high-speed memory system to hold data and/or processor instructions needed by the processing device. FIG. 1 depicts a typical memory system configuration 20. A host processor 22 issues data store and retrieve requests to a memory controller 24 over a front-side bus FSB. Memory controller 24 acts as an intermediary for the exchange of data between processor 22 and memory devices 26A and 26B. The memory controller performs memory transfers by relating the processor""s memory requests (into its view of a contiguous memory space) to the individual memory devices"" activation, addressing, timing, and bus signaling requirements. The memory controller""s techniques for partitioning and accessing the memory devices may be highly optimized in order to avoid wasted bus cycles; the controller may also perform memory management functions such as device initialization, refresh for memories that require refresh, etc.
Various circumstances can exist to cause any particular memory device""s duty cycle (i.e., the percent of the time that the device is actually performing memory operations) to be relatively low, either for brief periods (e.g., a microsecond) or for extended periods. For instance, the processor may be sleeping, lightly loaded, or successfully hitting an intermediate cache (and therefore not needing to access the main memory).
Normally, memory devices are maintained in a ready state that allows them to respond to a new request from a memory controller within a few clock cycles. In order to reduce power consumption, e.g., for battery-powered or energy-conserving devices, many existing memory devices offer a xe2x80x9cpower-downxe2x80x9d mode that deactivates input and output buffers and other clocked circuitry, without loss of data. During a time when a memory device is idle, the memory controller can instruct that device to enter the power-down mode, thereby saving a significant fraction of the device""s ready-state power.